A grid array package is a type of surface mount package used for integrated circuits. Two generic types of grid array packages are most common: ball grid arrays in which a small solder ball is used as the joining interface; and column grid arrays in which a cylindrical column of solder is used as the joining interface. In a typical ball grid array, balls or beads of solder are affixed to one face of the package in a grid pattern. The package is placed on a printed circuit board, which has tin- or solder-coated copper pads arranged in a pattern that matches the grid pattern of the solder balls. The solder balls are used to conduct electrical signals to and from an integrated circuit mounted in the package to the printed circuit board. When the solder is heated to a liquid state, the solder from the solder balls alloy with the material on the corresponding Printed Wiring Board (PWB) pads to effect a metallurgical and electrical bond. While the solder is in the liquid state, the surface tension of the molten solder holds the package in alignment with the printed circuit board and maintains separation from its neighbors while the solder cools and solidifies.
Grid array packages have numerous and significant advantages over other surface mount packages (e.g., leaded packages) for integrated circuits. For example, ball grid arrays can have much higher pin counts (generally 100 or more pins) per given area than prior packages and allow for higher packaging densities. Furthermore, due to the very short distances between their packages and the printed circuit boards, ball grid arrays have much lower thermal resistances and inductances than leaded packages. Thus, ball grid arrays provide much higher heat dissipation and electrical performance than prior surface mounted or other types of packages for integrated circuits.
Notwithstanding the distinct advantages of grid array packages, they are still prone to some of the same environmental sensitivities as their leaded counterparts (primarily moisture, radiation and heat). In addition, grid array packages tend to be more susceptible to contamination entrapment and solder bridging due to the close spacing and confined area in which the solder attachments are formed. However, due to the performance, cost and processing advantages of grid array packages, they are now entering the realm of high reliability electronic products. For example, the National Aeronautics and Space Administration (NASA) has approved the use of grid arrays as surface mount packages for integrated circuits in very long space missions with high reliability requirements. In an effort to further reduce cost, manufacturers have employed the use of plastic and polymeric materials in the outer packaging materials for grid array packages. This results in packages that are more susceptible to moisture and humidity than their ceramic counterparts. For this reason, plastic packages often require special handling, processing and storage conditions. In addition, high reliability applications may also have additional requirements that plastic packages have difficulty achieving. These requirements include radiation resistance, dielectric strength, out-gassing, off-gassing, flammability and atomic oxygen resistance that limit the choice of plastic materials that can be used for ball grid arrays. In order to help meet these special mission requirements, plastic grid array packages can be externally coated with a material such as parylene, to afford additional protection against these environments, that either minimize the special handling, processing and storage needs, or impart additional capabilities to the coated parts. Unfortunately, these coatings are typically applied after the part has been placed on the board, resulting in a difficult rework process if the part fails, and special handling and storage during the board build process. For this reason, development of a part-level coating process, that provides the required protection at the part level, and still allows for preliminary test and subsequent installation of the part, will reduce cost and improve reliability. Unfortunately, grid array packages are extremely difficult to coat in a truly conformal coating fashion at the part level due to the difficulty in isolating the individual grid array pads from the coating process.
Parylene is a polymer material of uniform thickness, which is often used for conformal coating of components with sharp edges, points, flat surfaces, crevices or exposed internal surfaces, uniformly and without voids. Parylene is applied using a molecular vapor deposition process in which heated molecules of the parylene dimmer are vaporized and deposited on the cooler substrate surfaces, resulting in a completely conformal coating. Parylene has an extremely high dielectric strength, a very low permeability to moisture and gases, virtually zero out-gassing, can withstand a wide temperature range, high radiation resistance, and provides a benign nonconductive, low stress coating for sensitive electronic circuitry (among other advantages). Thus, parylene is an excellent choice for conformal coating of grid array packages. However, a drawback of the use of parylene for coating grid array packages is the difficulty in achieving a coating-free condition on the solder attachment surfaces (given their relatively small size and tight spacing).
As a result, grid array packages are commonly coated after they have been soldered in place on the PWB. This technique results in: a.) the need to apply special handling, processing and storage requirements for the grid array packages during the build process to prevent moisture uptake from the environment and cleaning processes; b.) problems in obtaining a fully coated grid array surface due to the limited access of the grid array surface in the installed configuration; and c.) a rather involved and risky rework process to remove parts that fail during subsequent test and integration operations. Therefore, it would be advantageous to have a solution to this existing problem of coating grid array and similar types of packages for integrated circuits at the individual part level. As described in detail below, the present invention provides an improved method and apparatus that resolves this existing problem and other similar problems.